Principal Engineer – SoC Design Lead

📋 Description

• Responsible for developing logic design, register transfer level (RTL) coding, and simulation for an SoC design

• Integrating logic of IP blocks and subsystems into a full chip SoC or discrete component design

• Participating in defining architecture and microarchitecture features of the block being designed

• Performing quality checks in various logic design aspects ranging from RTL to timing/power convergence

• Applying strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals

• Reviewing the verification plan and implementation to ensure design features are verified correctly

• Following secure development practices to address the security threat model and security objects within the design

• Working with IP providers to integrate and validate IPs at the SoC level

• Driving quality assurance compliance for smooth IPSoC handoff

• Developing and mentoring other technical leaders

⛳️ Requirements

• MS or PhD in Electrical Engineering or related field

• 10+ years of hands-on experience in CPU, GPU, NOC architecture and emulation

• Proven leadership experience managing technical teams for 5+ years

• Exposure to AI compute architecture and learning algorithms

• Familiarity with a variety of EDA verification and validation tools

• Strong understanding of various types of industry standard SoC architecture and IPs

🏝️ Benefits

• Competitive pay

• Stock

• Bonuses

• Health

• Retirement

• Vacation